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ATmega128
Table 55. Compare Output Mode, Phase Correct P W M Mode (1)
COM01
0
0
1
1
COM00
0
1
0
1
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match when up-counting. Set OC0 on compare
match when downcounting.
Set OC0 on compare match when up-counting. Clear OC0 on compare
match when downcounting.
Note:
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. See “Phase Correct P W M Mode” on page
100 for more details.
? Bit 2:0 – CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Table
56 .
Table 56. Clock Select Bit Description
CS02
0
0
0
0
1
1
1
1
CS01
0
0
1
1
0
0
1
1
CS00
0
1
0
1
0
1
0
1
Description
No clock source (Timer/Counter stopped)
clk T0S /(No prescaling)
clk T0S /8 (From prescaler)
clk T0S /32 (From prescaler)
clk T0S /64 (From prescaler)
clk T0S /128 (From prescaler)
clk T 0 S /256 (From prescaler)
clk T 0 S /1024 (From prescaler)
Timer/Counter
Register – TCNT0
Bit
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. W riting to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.
Output Compare
Register – OCR0
Bit
7
6
5
4
3
2
1
0
OCR0[7:0]
OCR0
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC0 pin.
105
2467X–AVR–06/11
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